module regfile_and_decoder (/*AUTOARG*/
   // Outputs
   read_data1, read_data2, read_data3, read_data4,
   // Inputs
   clk, reset, regwrite1, regwrite2, write1_addr, write2_addr,
   read_data1_addr, read_data2_addr, read_data3_addr, read_data4_addr,
   write_data1, write_data2
   );

input clk;
input reset;
input regwrite1;
input regwrite2;
input [4:0] write1_addr;
input [4:0] write2_addr;
input [4:0] read_data1_addr;
input [4:0] read_data2_addr;
input [4:0] read_data3_addr;
input [4:0] read_data4_addr;
input [31:0] write_data1;
input [31:0] write_data2;
output[31:0] read_data1;
output[31:0] read_data2;
output[31:0] read_data3;
output[31:0] read_data4;

wire [31:0] write1_enables;
wire [31:0] write2_enables;
wire [31:0] ren1_enables;
wire [31:0] ren2_enables;
wire [31:0] ren3_enables;
wire [31:0] ren4_enables;


decoder write1_decoder (.in(write1_addr), .out(write1_enables));
decoder write2_decoder (.in(write2_addr), .out(write2_enables));

decoder read1_decoder (.in(read_data1_addr),.out(ren1_enables));
decoder read2_decoder (.in(read_data2_addr),.out(ren2_enables));
decoder read3_decoder(.in(read_data3_addr),.out(ren3_enables));
decoder read4_decoder (.in(read_data4_addr),.out(ren4_enables));

regfile regi (.clk(clk), .reset(reset),
.wen1(write1_enables),
.wen2(write2_enables),
.ren1(ren1_enables),
.ren2(ren2_enables),
.ren3(ren3_enables),
.ren4(ren4_enables),
.read_data1(read_data1),
.read_data2(read_data2),
.read_data3(read_data3),
.read_data4(read_data4),
.w_data1(write_data1),
.w_data2(write_data2),
.wr1(regwrite1),
.wr2(regwrite2));

endmodule
